// (C) Copyright 2012 Kystar. All rights reserved.

`timescale 1ns/100ps
`default_nettype none

module iddr_ctr
(
    input  wire          I_rgmii_px_rxc,
    input  wire          I_rgmii_px_rxdv,
    input  wire [  3: 0] I_rgmii_px_rxd,

    output wire          O_px_rxc,
    output wire          O_px_rxdv,
    output wire          O_px_rxer,
    output wire [  7: 0] O_px_rxd
);

RGMII_rec_io u_RGMII_rec_io(
    .rxc(I_rgmii_px_rxc),
    .rxdv(I_rgmii_px_rxdv),
    .rxd(I_rgmii_px_rxd),

    .rx_clk(O_px_rxc),
    .rx_dv(O_px_rxdv),
    .rx_data(O_px_rxd),

    .rx_er(O_px_rxer),
    .rx_crs(),
    .rx_col()
    );

endmodule
`default_nettype wire
